数字系统设计常见问题解答
- Explain the single stuck fault model. What are the limitations of this model?
SSFM assumes that a defect causes a node to be stuck at 1 or stuck at 0 and that only one node is affected (i.e. that faults don’t mask).
💡 解释一下单一卡住的故障模型。这个模型的局限性是什么？
SSFM假定一个缺陷导致一个节点卡在1或卡在0，并且只有一个节点受到影响（即故障不会掩盖）。
- Explain the difference between “one-hot” state assignment and binary state assignment. Why is one-hot assignment preferred in FPGA designs?
“One-hot” means one flip-flop per state. Exactly one flip-flop output is asserted in each clock cycle. Binary encoding means that the states are mapped to a minimum number of bits. The one-hot style is preferred in FPGAs because FPGAs are rich in flip-flops, but relatively poor in combinational logic. Binary encoding can require a lot of combinational logic. Using the combinational logic in a CLB means that the flip-flop cannot be used for anything else. At best, therefore, binary encoding uses the same number of CLBs as one-hot, but the flip-flops are wasted. In the worse case, more CLBs are used.
💡 解释 “one-hot”状态分配和二进制状态分配之间的区别。为什么在FPGA设计中倾向于“one-hot”式分配？
“one-hot”意味着每个状态有一个触发器。在每个时钟周期中，正好有一个触发器输出被断言。二进制编码意味着状态被映射到最小的比特数。在FPGA中，“one-hot”式是首选，因为FPGA有丰富的触发器，但在组合逻辑方面相对较差。二进制编码可能需要大量的组合逻辑。在CLB中使用组合逻辑意味着该触发器不能用于其他用途。因此，在最好的情况下，二进制编码使用的CLB数量与one-hot相同，但触发器被浪费了。在更糟糕的情况下，会使用更多的CLBs。
- Explain the sensitive path algorithm. How is it used in testing combinational circuits?
The sensitive path algorithm – a node is set to a value and that value is propagated to an output by sensitising paths. Only primary inputs are controlled. Only primary outputs are observed.
💡 解释一下敏感路径算法。它是如何用于测试组合电路的？
敏感路径算法 – 一个节点被设置为一个值，该值通过敏感路径传播到输出。只有主输入能控制。只有主输出能被观察到。
- Explain the difference between synchronous and asynchronous inputs to a sequential system. For what purpose should an asynchronous reset input be used?
Synchronous is with the clock. Asynchronous is independent of the clock and will override the clock. Asynchronous reset should only ever be used as a power-on reset.
💡 解释一下时序系统的同步和异步输入之间的区别。
异步复位输入应该用于什么目的？ 同步是与时钟同步。异步是独立于时钟的，并且会覆盖时钟。异步复位应该只作为开机复位使用。
- Explain the principle of Scan-In, Scan-Out (SISO).
The principle of SISO is to insert a multiplexer at the input of each flip-flop in a sequential circuit and to connect one input of each mux to the output of the preceding FF, such that the FFs may be configured as a shift register for testing purposes. This allows the combinational part of the circuit to be tested as if it were separated from the flip-flops.
💡 解释一下扫描输入、扫描输出（SISO）的原理。
SISO的原理是在顺序电路中每个触发器的输入端插入一个多路复用器，并将每个多路复用器的一个输入端连接到前一个FF的输出端，这样就可以将FF配置成一个移位寄存器，用于测试。这使得电路的组合部分可以被测试，就像它与触发器分离一样。
- A Binary Coded Decimal (BCD) counter counts from 0 to 9 (decimal) and then returns to 0. How many flip-flops are needed to implement this counter? How many unused values are there? Is it possible to predict what would happen if the counter entered an unused state (for example, as a result of a timing error) if the exact implementation is not known?
Need 4 flip-flops, 6 unused values. We don’t know exactly what would happen – it depends on how the next state logic is constructed. One possibility is that the counter gets stuck in the unused states.
💡 一个二进制编码的十进制（BCD）计数器从0计数到9（十进制），然后返回到0，实现这个计数器需要多少个触发器？有多少个未使用的值？如果不知道确切的实现方式，是否可以预测如果计数器进入未使用状态（例如，由于定时错误）会发生什么？
需要4个触发器，有6个未使用的值。我们不知道到底会发生什么–这取决于下一个状态逻辑是如何构建的。一种可能性是，计数器被卡在未使用的状态。
- Why is Assertion-Based Verification used in preference to other veri-fication methods?
Inspecting the waveforms produced by simulation is difficult and error-prone. ABV allows expectations to be stated (effectively higher level models). Thus information about the behaviour can be automatically returned. Assertions also allow the use of formal methods.
💡 为什么要使用基于断言的验证，而不是其他验证方法？
检查由模拟产生的波形是困难的，而且容易出错。ABV允许陈述期望值（有效的高层次模型）。因此，关于行为的信息可以自动返回。断言也允许使用形式化的方法。
- Explain what is meant by a vacuous assertion. How can you know whether an assertion has passed vacuously?
A vacuous assertion is one that can never fail. This may be a liveness property (something good happens eventually). The easiest way to detect a vacuous pass is to count how many times each assertion is tested, using the cover construct. If an assertion is never tested, it’s not very useful.
💡 解释一下空洞的断言是什么意思。你怎么能知道一个断言是否空洞地通过了？
一个空洞的断言是一个永远不会失败的断言。这可能是一种有效性属性（最终会有好的事情发生）。检测空洞通过的最简单方法是使用覆盖结构，计算每个断言被测试的次数。如果一个断言从未被测试过，那么它就没有什么用。
- Explain the principle of Assertion-Based Verification.
ABV means that the output of a design under test is checked against a reference to see whether it gives the right result at the right time. If not a warning is generated. Therefore a lot of correct simulation results can be ignored, cutting down the volume of data that has to be assessed by the design engineer.
💡 解释基于断言的验证的原理。
ABV是指将被测设计的输出与参照物进行检查，看它是否在正确的时间给出正确的结果。如果不是，就会产生一个警告。因此，很多正确的模拟结果可以被忽略，减少了设计工程师必须评估的数据量。
- What are the benefits of using Assertion Based Verification?
The main benefit of ABV is that it removes the need to inspect complicated waveforms in order to determine whether a design works correctly.
💡 使用基于断言的验证有什么好处？
ABV的主要好处是它消除了检查复杂波形以确定设计是否正确工作的需要。
- Describe a possible application of this hardware(LFSR).
A possible application is as a test generator for built-in self-test. It generates an almost exhaustive set of test patterns in a pseudo random sequence.
💡 描述硬件（LFSR）的可能应用。
一个可能的应用是作为内置自我测试的测试发生器。它产生了一个几乎 在一个伪随机序列中生成一套几乎详尽的测试模式。
- What features distinguish a SystemVerilog “testbench” from other SystemVerilog models?
Testbenches have no inputs or outputs. Testbenches have initial blocks to generate inputs to the DUT.
💡 SystemVerilog “Testbench” 与其他SystemVerilog模型的区别是什么？
Testbench没有输入或输出。Testbench有初始块来产生对测试设备的输入。
- Explain the SystemVerilog stratified event queue. How does this compare with the VHDL simulation model?
Stratified event queue has several regions including active, inactive and nonblocking assignments. Events from active region are processed. These include blocking assignments. New events at current time are added to one of the three queues. Inactive events are added after explicit zero delays. As the active event list is exhausted, inactive and nba events become active in turn. SV has the observe region for assertions and the reactive region for programs.
VHDL has the concept of delta times. A new event is always inserted into a queue at a later time – which might be one delta cycle in the future. In that way, races are avoided.
💡 解释一下SystemVerilog的分层事件队列。这与VHDL仿真模型相比有什么不同？
分层事件队列有几个区域，包括活动、非活动和非阻塞的分配。活动区域的事件被处理。这些包括阻塞的分配。当前时间的新事件被添加到三个队列中的一个。不活跃的事件在明确的零延迟后被添加。随着活动事件列表的耗尽，非活动和nba事件依次成为活动事件。SV有用于断言的观察区域和用于程序的反应区域。
VHDL有delta时间的概念。一个新的事件总是在以后的时间插入队列中–这可能是未来的一个delta周期。通过这种方式，可以避免竞赛。
- What is the Single-Stuck Fault Model? How is it used in testing combinational circuits?
The Single-Stuck Fault Model assumes that a defect is manifested as one node of the circuit being permanently stuck at logic 1 or at logic 0. Multiple faults do not cancel. SSFM is used in sensitive path algorithm – a node is set to a value and that value is propagated to an output by sensitising paths.
💡 什么是Single-Stuck Fault模型？它是如何用于测试组合电路的？
单一故障模型假定缺陷表现为电路的一个节点永久地停留在逻辑1或逻辑0处。多个故障不会抵消。SSFM用于敏感路径算法–一个节点被设置为一个值，该值通过敏感路径传播到输出。
- How would you test the scan-path for stuck-at faults? What is the consequence of a stuck-at fault in the scan-path?
The scan-path needs to be tested by applying a sequence, such as 0101 through the scan-path, when it is in scan-mode. If a stuck fault exists, only 0s or 1s will be observed at the scan output. Hence the circuit will be identified as faulty and rejected, even if the rest of the circuit functions correctly.
💡 你将如何测试扫描路径的卡住故障？在扫描路径中出现卡住的故障会有什么后果？
当扫描模式时，需要通过应用一个序列来测试扫描路径，例如0101通过扫描路径。如果存在卡住的故障，在扫描输出端将只观察到0或1。因此，即使电路的其他部分功能正常，该电路也会被认定为有故障而被拒绝。
- Why blocking assignments is not deterministic？
The code is not deterministic because blocking assignments are used. This means that the ordering of events in the event list is non-deterministic, so at a clock edge, it’s not known which flip-flop is evaluated first and hence whether the value before or after the clock edge is assigned in each case. The solution is to use nonblocking assignments. This ensures that the right hand sides are evaluated at the clock edge, but the assignments are not completed until after all blocking events have been done.
💡 为什么阻断赋值不是确定性的？
这段代码不是决定性的，因为使用了阻塞式赋值。这意味着事件列表中事件的排序是不确定的，所以在一个时钟边缘，不知道哪个触发器先被评估，因此在每种情况下，时钟边缘之前或之后的值被分配。 解决办法是使用非阻塞式分配。这可以确保右侧在时钟边缘被评估，但在所有阻塞事件完成后才完成赋值。
17. How might LFSR circuit be used in a built-in self-test (BIST) scheme?
The circuit is an LFSR. It generates a pseudo random, (nearly) exhaustive sequence. Thus it is a cheap way of generating test patterns on chip.
💡 LFSR电路如何在内置自检（BIST）方案中使用？
该电路是一个LFSR。它产生了一个伪随机的、（几乎）穷尽的序列。因此，它是一种在芯片上生成测试模式的廉价方法。
- How might the circuit enter an unused state? How can this be avoided?
If the enable input changes just before the clock edge, there would be a set-up time violation and the next state would be unpredictable.
This can be avoided by ensuring the clock speed is not too great. If the enable input comes from outside the clock domain (off-chip), it can be synchronised by putting it through two flip-flops. This catches any metastability.
💡 电路怎么能进入未使用的状态？怎样避免这种情况？
如果使能输入在时钟边沿之前发生变化，就会出现设置时间的违反，下一个状态将是不可预知的。 这可以通过确保时钟速度不要太大来避免。如果使能输入来自于时钟域之外（片外），可以通过将其置于两个触发器中来实现同步。这可以捕捉到任何偏移性。
- Explain why this assertion might be considered to be poorly designed?
V1: The assertion states that if the Start signal is asserted, the counter will return to the all 0s state eventually – i.e. an infinite number of clock cycles can pass. This is poorly designed assertion because it may never complete and hence it can never fail. In other words, it tells us nothing.
💡 解释一下为什么这个断言可能被认为是设计不良的？
V1: 该断言指出：如果 “开始 “信号被断言，计数器最终将返回到全部为0的状态–也就是说，可以通过无限多的时钟周期。 这是一个设计不良的断言，因为它可能永远不会完成，因此它永远不会失败。换句话说，它没有告诉我们什么。
V2: The assertion states that if the enable signal is asserted, the counter will reach state 1011 after 5 cycles. If this assertion were written to test whether the state is reached eventually, an infinite number of clock cycles could pass. This would be a poorly designed assertion because it may never complete and hence it can never fail. In other words, it would tell us nothing.
V2: 该断言指出：如果使能信号被断言，计数器将在5个周期后达到状态1011。如果这个断言被写成测试是否最终达到了状态，那么可能会有无限多的时钟周期通过。 这将是一个设计不良的断言，因为它可能永远不会完成，因此它不可能失败。换句话说，它不会告诉我们什么。
- What is the simplest modification that could be made to the circuit to make it completely testable? If the circuit were part of a larger synchronous sequential system, what effect would your modification have on the overall behavior of that system?
V1: To make the circuit testable, can remove the redundant gate. This removes the hazard protection, but this doesn’t matter in a synchronous system.
V2: Remove the gate at XXX. The gate is (presumably) there to protect against a static hazard. If the gate is removed the hazard can still exist, but in a synchronous circuit, this doesn’t matter as any glitch will finish before the next clock edge. And the circuit is simpler. No effect on testing.
💡 为了使该电路完全可测试，可以对其进行的最简单的修改是什么？如果该电路是一个更大的同步时序系统的一部分，你的修改会对该系统的整体行为产生什么影响？
V1: 为了使电路可测试，可以去掉多余的门。这就去掉了危险保护，但这在同步系统中并不重要。
V2: 移除XXX处的门。该门（大概）是为了防止静态危险而设置的。如果门被移除，危险仍然存在，但在同步电路中，这并不重要，因为任何故障都会在下一个时钟沿之前完成。而且电路也比较简单。对测试没有影响。
- Explain how a scan-path can be included within the circuit of Figure, such that only one additional input and no additional outputs are required. How would you test the scan path to ensure that it contains no faults? Explain how the test that you derived in parts (a) and (c) can be applied to the full, sequential circuit. What would be observed at the output of the scan-path if each of the faults J/1 and J/0 do not exist, and also each fault exists?
V1：Two multiplexers are inserted, before the D inputs of the flip-flops. Let’s assume that the additional input is control signal, M, which enables the scan path when 1. In scan mode, A (or B) is connected to the scan i/p of T; T is connected to S and the scan data output is S. Test the scan path by setting M to 0 and applying a sequence, 0, 1, 0, 1 to A (or B). We should see the same sequence at S, delayed by 2 clock cycles. To set S and T to 0, we set M to 1, A to 0 and clock twice. Then, set A to 1, set M to 0, clock once. This loads T+ and S+ into the scan chain. We can observe S+ at this point and observer any errors in that part of the combinational logic. Set M to 1, clock once. This moves T+ to S. We can now observe the value at S, so if J/1 does not exist, S is 1, otherwise S is 0. The second test can be applied in the same way: M=1, A=0, clock twice. Then keep A=0, M=0, clock once, M=1, clock once. For full marks, note that the two tests can be overlapped.
💡 解释一下如何在图中的电路中包含一个扫描路径，这样就只需要一个额外的输入，没有额外的输出。 你将如何测试扫描路径以确保它不包含故障？ 解释一下你在(a)和(c)部分得出的测试结果如何能应用于完整的顺序电路。如果每个故障J/1和J/0都不存在，而且每个故障都存在，在扫描路径的输出端会观察到什么？
V1：在触发器的D输入之前，插入两个多路复用器。让我们假设额外的输入是控制信号M，当其为1时启用扫描路径模式。在扫描模式下，A（或B）与T的扫描i/p相连；T与S相连，扫描数据输出为S。 通过将M设置为0并在A（或B）上应用一个序列，0，1，0，1来测试扫描路径。在延迟了2个时钟周期后，我们应该在S处可以看到相同的序列。 为了将S和T设置为0，我们将M设置为1，A设置为0，并经过两次时钟周期。 然后，将A设置为1，将M设置为0，再时钟一次。这就把T+和S+加载到扫描链中。我们可以在这一点上观察S+，并观察组合逻辑的这一部分的任何错误。 将M设置为1，经过一个时钟周期。现在我们可以观察S处的值，所以如果J/1不存在，S是1，否则S是0。 第二个测试可以以同样的方式应用。M=1，A=0，经过两次时钟周期。然后保持A=0，M=0，经过一次时钟周期；令M=1，在经过一次时钟周期。 注意：对于满分情况，这两个测试可以被等同对待。
V2：There are several ways to insert a scan path. Let’s assume that there is a control signal, B, which enables the scan path when 1. Assume, in scan mode, A is connected to the scan i/p of T; T is connected to S and the scan data output is S. (This is the easiest way to do it!) So, to set S and T to 1, we set B to 1, A to 1 and clock twice. Then, set A to 1 (or 0), set B to 0, clock once. This loads T+ and S+ into the scan chain. We can observe S+ at this point and observer any errors in that part of the combinational logic. Set B to 1, clock once. This moves T+ to S. We can now observe the value at S, so if M/1 does not exist, S is 1, otherwise S is 0.
V2：有几种方法可以插入扫描路径。假设有一个控制信号B，当1时启用扫描路径。假设在扫描模式下，A与T的扫描i/p相连；T与S相连，扫描数据输出是S。（这是最简单的方法！）。 因此，为了将S和T设置为1，我们将B设置为1，A设置为1，并进行两次时钟。 然后，将A设置为1（或0），将B设置为0，时钟一次。这就把T+和S+加载到扫描链中。我们可以在这一点上观察S+，并观察组合逻辑的这一部分的任何错误。 设置B为1，时钟一次。现在我们可以观察S的值，如果M/1不存在，S就是1，否则S就是0。
